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International Power Electronics Congress - CIEP
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type: Generically Dependent Continuant
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publication venue for: PWM switching patterns optimization for multilevel inverter using a FPGA

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RDF description of PWM switching patterns optimization for multilevel inverter using a FPGA - http://orbis.uaslp.mx/vivo/individual/scopus8285
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date: 2026-08-28T03:09:25
publisher: vivo
type: Document

Article
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PWM switching patterns optimization for multilevel inverter using a FPGA
type: Entity
type: Thing
page start: 207
type: Information Content Entity
most specific type: Document
has publication venue: International Power Electronics Congress - CIEP
EI dscopus: 2-s2.0-28744454599
related by: authorship_53103
most specific type: Conference Paper
related by: authorship_53105
freetext keyword: Electric inverters; Electric potential; Field programmable gate arrays; Optimization; Signal processing; Control signals; Switching patterns; Pulse width modulation
crisid: 8286
related by: authorship_53104
date time value: conference paper date 8286
abstract: This paper presents the implementation on a Field Programmable Gate Array (FPGA) of a PWM Switching Patterns Optimization for a voltage multilevel inverter. FPGA is used for generating of the switching patterns and dead time for a cascaded multilevel inverter. The design uses a PWM sinusoidal in order to have a control signal to generate the signals remaining. These signals are developed by delays applied to control signal. Useful advantages of this scheme arc easy implementation, software control and flexibility in adaptation to generate many output voltage levels Simulations and experimental results are included. © 2004 IEEE.
related by: authorship_53102
type: Article
type: Generically Dependent Continuant
type: Document
page end: 211
estado: published
type: Continuant
type: Conference Paper
origen: scopus

Conference Paper
type: Class