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International Power Electronics Congress - CIEP
Generically Dependent Continuant
RDF description of PWM switching patterns optimization for multilevel inverter using a FPGA - http://orbis.uaslp.mx/vivo/individual/scopus8285
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PWM switching patterns optimization for multilevel inverter using a FPGA
Electric inverters; Electric potential; Field programmable gate arrays; Optimization; Signal processing; Control signals; Switching patterns; Pulse width modulation
This paper presents the implementation on a Field Programmable Gate Array (FPGA) of a PWM Switching Patterns Optimization for a voltage multilevel inverter. FPGA is used for generating of the switching patterns and dead time for a cascaded multilevel inverter. The design uses a PWM sinusoidal in order to have a control signal to generate the signals remaining. These signals are developed by delays applied to control signal. Useful advantages of this scheme arc easy implementation, software control and flexibility in adaptation to generate many output voltage levels Simulations and experimental results are included. © 2004 IEEE.
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