Document
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2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
type: Book
type: Information Content Entity
type: Document
type: Continuant
type: Thing
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publication venue for: Hybrid multiplierless FIR filter architecture based on NEDA
type: Generically Dependent Continuant
type: Proceedings

Hybrid multiplierless FIR filter architecture based on NEDA
type: Document
has publication venue: 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
page start: 316
date time value: conference paper date 7644
EI dscopus: 2-s2.0-50149108401
estado: published
type: Information Content Entity
most specific type: Conference Paper
origen: scopus
most specific type: Document
freetext keyword: Impulse response; LSI circuits; Programmable logic controllers; Adder tree; Critical Paths; Design methods; Distributed arithmetic; Fan-out; Finite-impulse response; FIR filter architecture; Hybrid structures; International conferences; Multiplierless; Proposed architectures; Trade offs; Very large-scale integration; FIR filters
doi: 10.1109/VLSISOC.2007.4402521
type: Thing
type: Continuant
crisid: 7644
related by: authorship_48781
type: Article
type: Conference Paper
artnum: 4402521
type: Entity
type: Generically Dependent Continuant
page end: 319
related by: authorship_48780
related by: authorship_48779
abstract: This paper presents new hybrid multiplierless finite impulse response (FIR) architecture based on New Distributed Arithmetic (NEDA). The hybrid structure is a trade off between direct form and transposed direct form that results in a reduction of the critical path and the size of the delays elements as well as the fan-out. While the multiplications involved in the hybrid structure are replaced by a butterfly adder tree. Compared with previous methods, our proposed architecture achieves an average of 20%25 less additions. Moreover, the design method is simple and achieves better results than previous methods. © 2007 IEEE.

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date: 2026-08-27T08:34:15
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Conference Paper
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