CMOS digital pixel for binary morphological edge segmentation Conference Paper

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Overview

abstract

• A digital pixel for binary morphological image processing is presented. The pixel is designed to be integrated into a vision chip with parallel architecture, in order to compute edge segmentation. The pixel contains 11 transistors working with analog signal and 20 transistor working with digital signal; pixel layout size is 115.2μm x 89.4μm; fill factor is 1.85%25; 1.2μm CMOS standard technology from AMI is used for prototyping; random noise is 2.7m V; peak analog output signal to noise ratio is 44dB; optical dynamic range is 53dB; dark current is 11mV/s; processing time is 3.5 ms; maximum power dissipation is 264 μW. © 2007 IEEE.

authors

• Garcia-Lamont J.
• Gonzalez-Vidal J.L.
• Sánchez Díaz Guillermo
• Vazquez-Acosta E.N.

publication date

• 2007-01-01

published in

• Electronics, Robotics and Automotive Mechanics Conference, CERMA 2007 - Proceedings  Proceedings

Research

keywords

• Analog to digital conversion; Automation; Automobile electronic equipment; Automobile parts and equipment; CMOS integrated circuits; Computer graphics; Digital arithmetic; Digital signal processing; Digital to analog conversion; Image processing; Imaging systems; Imaging techniques; Optical data processing; Signal to noise ratio; Speed; Standards; Analog signals; Automotive Mechanics; Digital pixels; Digital signals; Dynamic range (DR); Edge segmentation; Fill factor (FF); Maximum power dissipation; Morphological image processing; Optical (PET) (OPET); Output signal to noise ratio (SNR); Parallel architectures; Processing Time; Prototyping; Random noises; Standard technology; Vision chips; Pixels

Identity

Digital Object Identifier (DOI)

• 10.1109/CERMA.2007.4367697

Additional Document Info

start page

• 266

end page

• 270