Lightweight security hardware architecture using DWT and AES algorithms

The great increase of the digital communications, where the technological society depends on applications, devices and networks, the security problems motivate different researches for providing algorithms and systems resistant to attacks, and these lasts need of services of confidentiality, authentication, integrity, etc. This paper proposes the hardware implementation of an steganographic/cryptographic algorithm, which is based on the DWT (Discrete Wavelet Transform) and the AES (Advanced Encryption Standard) cipher algorithm in CBC mode. The proposed scheme takes advantage of a double-security ciphertext, which makes difficult to identify and decipher it. The hardware architecture reports a high efficiency (182.2 bps/slice and 85.2 bps/LUT) and low hardware resources consumption (867 slices and 1853 LUTs), where several parallel implementations can improve the throughout (0.162 Mbps) for processing large amounts of data. © 2018 The Institute of Electronics, Information and Communication Engineers.

Cryptography; DWT; FPGA; Hardware; Steganography Computer hardware; Cryptography; Data privacy; Digital communication systems; Digital devices; Discrete wavelet transforms; Field programmable gate arrays (FPGA); Hardware security; Network architecture; Network security; Public key cryptography; Signal reconstruction; Steganography; Advanced Encryption Standard; Digital communications; DWT (discrete wavelet Transform); Hardware architecture; Hardware implementations; Large amounts of data; Lightweight securities; Parallel implementations; Hardware

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